1. Field of the Invention
The present invention relates to a crimp-type power semiconductor device having an alloy-free structure wherein a semiconductor substrate and an electrode member are not soldered and which is suitable for use as a gate turn-off (GTO) thyristor, a reverse-blocking triode-thyristor (SCR) or a power transistor.
2. Description of the Related Art
A crimp-type semiconductor device, such as a gate turn-off thyristor (hereinafter referred to as a GTO thyristor), a reverse-blocking triode-thyristor (SCR) or a power transistor, is in general use as a power element. Such a semiconductor device will be explained with reference to FIGS. 1 and 2, taking an anode-shorted GTO thyristor by way of example In the descriptions below, the p- and n-conductivity types will be referred to as the first and second conductivity types, respectively.
Referring to FIG. 1, a disk-shaped, silicon semiconductor substrate 1 is prepared by alternately stacking semiconductor layers of different conductivity types one upon another. Specifically, the semiconductor substrate 1 is made up of first-conductivity type emitter layers 1a, a second-conductivity type base layer 1b, a first-conductivity type base layer 1c and second-conductivity type emitter layers 1d, and these semiconductor layers 1a-1d are arranged in the order mentioned from the side of the first major surface 2 (i.e., the bottom side) to the side of the second major surface 3 (i.e., the top side). The first major surface 2 serves as an anode region of a semiconductor element which is to be formed on the semiconductor substrate 1. In the plane of the first major surface 2, the first-conductivity type emitter layers 1a and the second-conductivity type base layer 1b are exposed, thereby providing a short-circuited structure. The second-conductivity type emitter layers 1d are projected upward from the second major surface 3, thereby providing a so-called mesa structure.
As is shown in FIG. 1, a second main electrode 4 is formed on top of each second-conductivity type emitter layer 1d. A control electrode 5 (i.e., a gate electrode) is formed on those surface portions of the first-conductivity type base layer 1c which are located between adjacent ones of the second-conductivity type emitter layers 1d.
A first main electrode 6, made of e.g. aluminum, is formed on the first major surface 2 of the semiconductor substrate 1, thereby providing a so-called anode-shorted structure.
As is shown in FIG. 1, a second electrode member 7E is arranged with reference to the second main electrodes 4 in an alloy-free state. Likewise, a first electrode member 8 is arranged with reference to the first main electrode 6 in an alloy-free state. The second electrode member 7E is made up of a temperature compensation plate 9 (i.e., a buffer plate against heat) and a soft-metal thin plate 10. The temperature compensation plate 9 is formed of high-melting point metal whose coefficient of thermal expansion is nearly equal to that of Si. For example, it is formed of W or Mo. The soft-metal thin plate 10 is formed of soft metal, such as Al, Ag, or Cu. The temperature compensation plate 9 and the soft-metal thin plate 10 are in contact with each other, and the soft-metal thin plate 10 is in contact with the second main electrodes 4. Incidentally, the soft-metal thin plate 10 need not be a single-layer structure; it may be a laminated structure made up of a plurality of foils.
The first electrode member 8 is formed of high-melting point metal whose coefficient of thermal expansion is nearly equal to that of Si. For example, it is formed of W or Mo. It is kept in contact with the first main electrode 6. A first electrode post 11 and a second electrode post 12, each of which is formed of Cu, are laid over the first electrode member 8 and the temperature compensation plate 9, respectively, such that the semiconductor substrate 1 is held in a strongly-pressed state. In FIG. 1, the first and second electrode posts 11 and 12 are depicted as having diameters substantially equal to those of the temperature compensation plates 8 and 9. In general, however, the diameters of the first and second electrode posts 11 and 12 are determined such that they are equal to, or shorter than the diameter of the semiconductor substrate 1.
In order to make the strongly-pressed state of the substrate 1 satisfactory, the second electrode member 7E is made up of two plates (namely, the temperature compensation plate 9 and the soft-metal thin plate 10), as mentioned above. In addition, the second electrode post 11 is made to have a different shape from that of the first electrode post 11, such that a spring member 13 and a gate lead section 14 (both of which will be mentioned later) can be provided.
As is apparent from FIG. 1, the second electrode post 12 has a step section which is formed by partly cutting out the post 12 from the center to the periphery. An insulating member 15 is located at that position of the step section which corresponds to the control electrode 5. A positioning guide 16 is located at both ends of the insulating member 15. At one end of the gate lead section 14, a conductive member 17 whose size is determined in accordance with the shape of the control electrode 5 is located. The conductive member 17 has a short-diameter straight portion 18 which linearly extending upward, and an extension portion 19 which is bent at right angels to the straight portion 18 and which extends to the outside of the device through an envelope 19-B (which is formed of ceramics or the like). At the other end of the gate lead section 14, a metallic sleeve 19-A soldered to the envelope 19-B is provided. Through this metallic sleeve 19-B, the gate lead section 14 is led to an external region. In order for the semiconductor substrate 1 (which is sandwiched between the second electrode member 7E and the first electrode member 8) to be pressed with a predetermined pressure, the spring member 13 is attached to the insulating member 15. A coil spring, a disk spring, or the like is used as the spring member 13.
The side faces of the semiconductor substrate 1 are beveled. After being subjected to etching treatment, the beveled surfaces are covered with silicone resin 19-C, for encapsulation. Finally, the flanges of the first and second electrode posts 11 and 12 are coupled to the envelope 19-B by soldering, thereby completing the fabrication of the anode-shorted GTO thyristor.
FIG. 2A is a partial plan view of the second major surface 3 of the semiconductor substrate 1, and conceptually illustrates the positional relationships between the second main electrodes 4 (indicated with solid lines) and the second electrode post 12 (indicated with broken lines). As can be seen from FIG. 2A, the second main electrodes 4 are formed on the respective second-conductivity type emitter layers 1d which are radially arranged on the first-conductivity type base layer 1c.
FIG. 2B illustrates a case where the second main electrodes 4 are arranged in parallel to one another. Like FIG. 2A, FIG. 2B is a partial plan view of the second major surface 3 of the semiconductor substrate and conceptually illustrates the positional relationships between the second main electrodes 4 (indicated with solid lines) and the second electrode post 12 (indicated with broken lines). Incidentally, reference symbol x indicates those portions of the second main electrodes 4 which are out of the range of the second electrode post 12.
As is shown in FIG. 1, the second electrode post 12 is provided with a cutaway section 12A. This cutaway section 12A is formed at a predetermined slanting angle at the periphery of the surface which is in contact with the second electrode member 7E. When the second electrode post 2 is strongly pressed against the second main electrodes 4, with the second electrode member 7E interposed, the cutaway section 12A prevents largely-different forces from being exerted to the end portion of the second main electrodes 4.
In the GTO thyristor shown in FIG. 1, the second electrode post 12 does not have a satisfactory heat-radiating characteristic at those portions which are not pressed, with the second electrode member 7E interposed, against the second main electrodes 4, i.e., at the portions indicated by reference symbol x in FIGS. 2A and 2B.
In addition, in the case where the second electrode post 12 and the second main electrodes 4 are arranged and positioned in the manner illustrated in FIGS. 2A and 2B, a current flow occurs concentratedly at the ends of the regions on which a strong force is exerted. As a result, the ability to withstand a surging current, an excessive amount of turn-off current, etc. deteriorates.
More specifically, the second main electrodes 4 are partly pressed by the second electrode post 12. In other words, the second main electrodes 4 include those portions which are not pressed by the second electrode post 12. Due to the existence of such portions, the current produced inside the semiconductor substrate 1 flows concentratedly into the end portions of the second electrode post 12, increasing the electric resistance of the end portions. Further, the heat generated in the semiconductor substrate 1 is transmitted to the end portions of the second electrode post 12. As a result, the thermal resistance of the region Y indicated in FIG. 1 increases, resulting in insufficient heat radiation.
As may be understood from the above, heat is generated concentratedly in the region Y when the GTO thyristor is turned off. Thus, it may happen that the GTO thyristor will be damaged due to the generation of such a hot spot in the semiconductor substrate 1.